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Freescale Semiconductor Data Sheet: Advance Information
Document Number: MC9RS08KA8 Rev. 1 , 1/2008
MC9RS08KA8
TBD MC9RS08KA8 Series
Covers: MC9RS08KA8
Features: * 8-Bit RS08 Central Processor Unit (CPU) - Up to 20 MHz CPU at 1.8 V to 5.5 V across temperature range of -40C to 85C - Subset of HC08 instruction set with added BGND instruction * On-Chip Memory - 8 KB flash read/program/erase over full operating voltage and temperature; KA4 has 4 KB flash - 254 byte random-access memory (RAM); KA4 has 126 byte RAM - Security circuitry to prevent unauthorized access to RAM and flash contents * Power-Saving Modes - Wait and stop - Wakeup from power-saving modes using real-time interrupt (RTI), KBI, or ACMP * Clock Source Options - Oscillator (XOSC) -- Loop-Control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 1 MHz to 5 MHz - Internal Clock Source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies up to 10 MHz * System Protection - Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock - Low-Voltage detection with reset or interrupt - Illegal opcode detection with reset - Illegal address detection with reset - Flash block protection * Development Support
20-Pin W-SOIC Case 751D
TBD TBD
16-Pin W-SOIC Case 751G
TBD
20-Pin PDIP Case 738C
16-Pin PDIP Case 648
- Single-Wire background debug interface - Breakpoint capability to allow single breakpoint setting during in-circuit debugging * Peripherals - ADC -- 12-channel, 10-bit resolution; 2.5 s conversion time; automatic compare function; operation in stop; fully functional from 2.7 V to 5.5 V (8-channels available on 16-pin package) - TPM -- One 2-channel; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel - IIC -- Inter-Integrated circuit bus module capable of operation up to 100 kbps with maximum bus loading; capable of higher baudrates with reduced loading - MTIM1 and MTIM2 -- Two 8-bit modulo timers - KBI -- Keyboard interrupts with rising or falling edge detect; eight KBI ports in 16-pin and 20-pin packages - ACMP -- Analog comparator: full rail-to-rail supply operation; option to compare to fixed internal bandgap reference voltage; can operate in stop mode * Input/Output - 14/18 GPIOs including one output only pin and one input only pin - Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins * Package Options - 16-pin, 20-pin SOIC or PDIP
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary--Subject to Change Without Notice
Table of Contents
1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .6 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .7 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18 3.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . . 3.10 Analog Comparator (ACMP) Electrical . . . . . . . . . . . . 3.11 Internal Clock Source Characteristics . . . . . . . . . . . . . 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 3.14.2 Conducted Transient Susceptibility . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 20 21 21 23 26 26 26 28 28
4 5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision 1
Date 1/22/2008 Initial public release
Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual (MC9RS08KA8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9RS08KA8 Series, Rev. 1 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
RS08 CORE CPU BDC IIC MODULE(IIC) ANALOG COMPARATOR (ACMP) 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) KEYBOARD INTERRUPT 16-BIT TIMER/PWM MODULE (TPM) 8-BIT TIMER (MTIM1 and MTIM2) PORT B PORT A PTA5/TCLK/RESET/VPP PTA4/ACMPO/BKGD/MS PTA3/KBIP3/SCL/ADP3 PTA2/KBIP2/SDA/ADP2 PTA1/KBIP1/TPMCH1/ADP1/ACMP- PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1 PTB4/TPMCH0 PTB3/KBIP7/ADP7 PTB2/KBIP6/ADP6 PTB1/KBIP5/ADP5 PTB0/KBIP4/ADP4 PTC3/ADP11 PORT C PTC2/ADP10 PTC1/ADP9 PTC0/ADP8
The block diagram, Figure 1, shows the structure of the MC9RS08KA8 MCU.
RS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP WAKEUP USER FLASH VPP (MC9RS08KA8 = 8192 BYTES) (MC9RS08KA4 = 4096 BYTES) USER RAM (MC9RS08KA8 = 254 BYTES) (MC9RS08KA4 = 126 BYTES) 20-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 39.0625 kHz 1 MHz to 5 MHz (XOSC) VSS VDD VOLTAGE REGULATOR RTI LVD
Figure 1. MC9RS08KA8 Series Block Diagram
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9RS08KA8 series.
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2
<-- Lowest Port Pin PTA5 PTA4 ACMPO Alt 1
Priority Alt 2
--> Highest Alt 3 RESET MS VDD VSS VPP Alt 4
16 1 2 3 4 5 6 7 8 -- -- -- -- 9 10 11 12 13 14 15 16
TCLK BKGD
PTB7 PTB6 PTB5 PTB4 PTC3 PTC2 PTC1 PTC0 PTB3 PTB2 PTB1 PTB0 PTA3 PTA2 PTA1 PTA0
SCL1 SDA
1 2
EXTAL XTAL
TPMCH1
TPMCH02 ADP11 ADP10 ADP9 ADP8 KBIP7 KBIP6 KBIP5 KBIP4 KBIP3 KBIP2 KBIP1 KBIP0 SCL1 SDA1 TPMCH1 TPMCH0
2 2
ADP7 ADP6 ADP5 ADP4 ADP3 ADP2 ADP1 ADP0 ACMP- ACMP+
IIC pins can be remapped to PTA3 and PTA2 TPM pins can be remapped to PTA0 and PTA1
PTA5/TCLK/RESET/VPP PTA4/ACMPO/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1 PTB4/TPMCH0 PTC3/ADP11 PTC2/ADP10
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/TPMCH1/ADP1/ACMP- PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/ADP4 PTB1/KBIP5/ADP5 PTB2/KBIP6/ADP6 PTB3/KBIP7/ADP7 PTC0/ADP8 PTC1/ADP9
Figure 2. MC9RS08KA8 Series in 20-Pin PDIP/SOIC Package
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Electrical Characteristics
PTA5/TCLK/RESET/VPP PTA4/ACMPO/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1 PTB4/TPMCH0
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/TPMCH1/ADP1/ACMP- PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/ADP4 PTB1/KBIP5/ADP5 PTB2/KBIP6/ADP6 PTB3/KBIP7/ADP7
Figure 3. MC9RS08KA8 Series in 16-Pin PDIP/SOIC Package
3
3.1
Electrical Characteristics
Introduction
This chapter contains electrical and timing specifications for the MC9RS08KA8 series of microcontrollers available at the time of publication.
3.2
Parameter Classification
Table 2. Parameter Classifications P C
Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
T D
NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this chapter.
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
Electrical Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 3. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to 5.8 120 -0.3 to VDD + 0.3 25 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD except the RESET/VPP pin which is internally clamped to VSS only. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance 16-pin PDIP Thermal resistance 16-pin SOIC Thermal resistance 20-pin PDIP Thermal resistance 20-pin SOIC TA TJMAX JA JA JA JA Symbol TL to TH -40 to 85 105 80 112 75 96 Value C C C/W C/W C/W C/W Unit
The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C
MC9RS08KA8 Series, Rev. 1 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Eqn. 1
Electrical Characteristics
JA = Package thermal resistance, junction-to-ambient, C /W
PD = Pint + PI/O Pint = IDD x VDD, Watts chip internal power PI/O = Power dissipation on input and output pins user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JAx (PD)2 Eqn. 3 Eqn. 2
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 5. ESD and Latch-up Test Conditions Model
Human Body
Description
Series resistance Storage capacitance Number of pulses per pin Series resistance
Symbol
R1 C -- R1 C -- -- --
Value
1500 100 3 0 200 3 -2.5 7.5
Unit
pF -- pF -- V V
Machine
Storage capacitance Number of pulses per pin Minimum input voltage limit
Latch-up Maximum input voltage limit
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics No.
1 2 3
Rating1
Human body model (HBM) Machine model (MM) Charge device model (CDM) Latch-up current at TA = 85C (applies to all pins except pin 9 PTC3/ADP11) Latch-up current at TA = 85C (applies to pin 9 PTC3/ADP11)
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 1002 753
Max
-- -- -- --
Unit
V V V mA
4
ILAT
--
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 2 These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of 100mA. 3 This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to 75mA. This pin is only present on 20 pin package types.
3.6
DC Characteristics
Table 7. DC Characteristics
(Temperature Range = -40 to 85C Ambient) Parameter Symbol VDD VRAM VLVD VPOR1 VIH VIH VIL VIL Vhys1 |IIn| |IOZ| RPU RPD -- Min 1.8 0.81 1.80 1.88 0.9 0.70 x VDD 0.85 x VDD -- -- 0.06 x VDD -- -- 20 20 45 Typical -- -- 1.86 1.94 -- -- -- -- -- -- 0.025 0.025 45 45 -- Max 5.5 -- 1.95 2.03 1.7 -- -- 0.30 x VDD 0.30 x VDD -- 1.0 1.0 65 65 95 Unit V V V V V V V V V A A k k k
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes.
Supply voltage (run, wait and stop modes.) 0 < fBus <10MHz Minimum RAM retention supply voltage applied to VDD Low-voltage Detection threshold (VDD falling) (VDD rising) Power on RESET (POR) voltage Input high voltage (VDD > 2.3V) (all digital inputs) Input high voltage (1.8 V VDD 2.3 V) (all digital inputs) Input low voltage (VDD > 2.3 V) (all digital inputs) Input low voltage (1.8 V VDD 2.3 V) (all digital inputs) Input hysteresis (all digital inputs) Input leakage current (per pin) VIn = VDD or VSS, all input only pins High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output Internal pullup resistors2(all port pins) Internal pulldown resistors2(all port pins except PTA5) PTA5 Internal pulldown resistor
MC9RS08KA8 Series, Rev. 1 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics
(Temperature Range = -40 to 85C Ambient) Parameter Output high voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = 2 mA 3 V, ILoad = 1 mA 1.8 V, ILoad = 0.5 mA Output high voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = 5 mA 3 V, ILoad = 3 mA 1.8 V, ILoad = 2 mA Maximum total IOH for all port pins Output low voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = 2 mA 3 V, ILoad = 1 mA 1.8 V, ILoad = 0.5 mA Output low voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = 5 mA 3 V, ILoad = 3 mA 1.8 V, ILoad = 2 mA Maximum total IOL for all port pins DC injection VIn < VSS, VIn > VDD Single pin limit Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins)
1 2 3 4 5 6
Symbol
Min
Typical -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 40
Unit
VDD - 0.8 VOH VDD - 0.8 |IOHT| -- -- -- -- -- -- -- IOLT --
V
mA
0.8 V 0.8 40 mA
VOL
current3, 4, 5 ,6
-- -- CIn --
-- -- --
0.2 0.8 7
mA mA pF
This parameter is characterized and not tested on each device. Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP which is internally clamped to VSS only. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. This parameter is characterized and not tested on each device.
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 5.5 V
-50 -40 IOH (mA) -30 -20 -10 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD-VOH (V) 85C 25C -40C
Figure 4. Typical IOH vs. VDD-VOH VDD = 5.5 V (High Drive)
IOH vs VDD-VOH (Low Drive) at VDD = 5.5 V
-12 -10 IOH (mA) -8 -6 -4 -2 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD-VOH (V) 85C 25C -40C
Figure 5. Typical IOH vs. VDD-VOH VDD = 5.5 V (Low Drive)
MC9RS08KA8 Series, Rev. 1 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 3 V
-20 IOH (mA) -15 -10 -5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VDD-VOH (V) 85C 25C -40C
Figure 6. Typical IOH vs. VDD-VOH VDD = 3 V (High Drive)
IOH vs VDD-VOH (Low Drive) at VDD = 3 V
-5 -4 IOH (mA) -3 -2 -1 0 0.2 0.4 0.6 0.8 VDD-VOH (V) 1.0 1.2 1.4 85C 25C -40C
Figure 7. Typical IOH vs. VDD-VOH VDD = 3 V (Low Drive)
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 1.8 V
-7 -6 -5 -4 -3 -2 -1 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VDD-VOH (V)
IOH (mA)
85C 25C -40C
Figure 8. Typical IOH vs. VDD-VOH VDD = 1.8 V (High Drive)
IOH vs VDD-VOH (Low Drive) at VDD = 1.8 V
-1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VDD-VOH (V)
IOH (mA)
85C 25C -40C
Figure 9. Typical IOH vs. VDD-VOH VDD = 1.8 V (Low Drive)
MC9RS08KA8 Series, Rev. 1 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 5.5 V
50 40 IOL (mA) 30 20 10 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOL (V)
c
85C 25C -40C
Figure 10. Typical IOL vs. VDD-VOL VDD = 5.5 V (High Drive)
IOL vs VOL (Low Drive) at VDD = 5.5 V
15 IOL(mA) 10 5 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOL (V) 85C 25C -40C
Figure 11. Typical IOL vs. VDD-VOL VDD = 5.5 V (Low Drive)
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 3 V
20 IOL (mA) 15 10 5 0 0.1 0.2 0.4 0.6 VOL (V) 0.8 1.0 1.2 1.4 85C 25C -40C
Figure 12. Typical IOL vs. VDD-VOL VDD = 3 V (High Drive)
IOL vs VOL (Low Drive) at VDD = 3 V
5 4 IOL (mA) 3 2 1 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VOL (V) 85C 25C -40C
Figure 13. Typical IOL vs. VDD-VOL VDD = 3 V (Low Drive)
MC9RS08KA8 Series, Rev. 1 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 1.8 V
5 4 IOL (mA) 3 2 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VOL (V) 85C 25C -40C
Figure 14. Typical IOL vs. VDD-VOL VDD = 1.8 V (High Drive)
IOL vs VOL (Low Drive) at VDD = 1.8 V
1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VOL(V)
IOL(mA)
85C 25C -40C
Figure 15. Typical IOL vs. VDD-VOL VDD = 1.8 V (Low Drive)
3.7
Supply Current Characteristics
Table 8. Supply Current Characteristics
Parameter Symbol VDD (V) 5 Typical1 2.4 mA 2.4 mA 1.7 mA Max2 5 mA -- -- Temp. (C) 25 85 25 85 25 85
Run supply current3 measured at (fBus = 10 MHz)
RIDD10
3 1.80
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Parameter Symbol VDD (V) 5 Run supply current3 measured at (fBus = 1.25 MHz) RIDD1 3 1.80 5 Stop mode supply current SIDD 3 1.80 5 ADC adder from stop4 3 1.80 5 ACMP adder from stop (ACME = 1) 3 1.80 5 RTI adder from stop with 1 kHz clock source enabled5 3 1.80 5 RTI adder from stop with 1 MHz external clock source reference enabled 3 1.80 5 LVI adder from stop (LVDE=1 and LVDSE=1) 3 1.80
1 2
Typical1 0.42 mA 0.42 mA 0.3 mA 2.4 A 2 A 1.5 A 128 A 121 A 79 A 21 A 18.5 A 17.5 A 2.4 A 1.9 A 1.5 A 2.1 A 1.6 A 1.2 A 70 A 65 A 60 A
Max2 2 mA -- -- 5 A 8 A -- -- 150 A 165 A -- -- 22 A -- -- 2 A -- -- 2 A -- -- 80 A -- --
Temp. (C) 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85
Typicals are measured at 25C. Maximum value is measured at the nominal VDD voltage times 10% tolerance. Values given here are preliminary estimates prior to completing characterization. 3 Not include any DC loads on port pins. 4 Required asynchronous ADC clock and LVD to be enabled.
MC9RS08KA8 Series, Rev. 1 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
5
Most customers are expected to find that auto-wakeup from stop can be used instead of the higher current wait mode. Wait mode typical is 1.3 mA at 3 V and 1 mA at 2 V with fBus = 1 MHz.
Run IDD vs VDD at FEI mode
3.00 2.50 2.00 VDD (V) 10 MHz 1.50 1.00 0.50 0.00 5.5 5.0 3.3 3.0 2.7 2.0 1.8 1.7 Run IDD (A) 4 MHz 1.25 MHz
Figure 16. Typical Run IDD vs. VDD for FEI Mode
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Electrical Characteristics
3.8
Num C
External Oscillator (XOSC) Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = -40 to 125C Ambient)
Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode 2 High range (RANGE = 1, HGO = 1) FBELP mode High range (RANGE = 1, HGO = 0) FBELP mode Load capacitors Feedback resistor Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 3 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)4 High range, high gain (RANGE = 1, HGO = 1)4 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode 2 FBELP mode Symbol flo fhi fhi-hgo fhi-lp C1, C2 Min 32 1 1 1 Typical1 Max -- -- -- -- Unit
1
C
38.4 kHz 5 MHz 16 MHz 8 MHz
2
D
See crystal or resonator manufacturer's recommendation. -- -- -- -- -- -- -- -- 10 1 0 100 0 0 0 0 200 400 5 -- -- -- -- -- -- -- -- 0 10 20 -- -- -- -- 5 40 M
3
D
RF
4
D
RS
k
5
C
t
t CSTL-LP CSTL-HGO t CSTH-LP
t CSTH-HGO
-- -- -- -- 0.03125 0
ms
6
1 2
D
fextal
MHz
Typical data was characterized at 5.0 V, 25C or is recommended value. The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 4 4 MHz crystal.
MCU EXTAL XTAL RS
RF
C1
Crystal or Resonator
C2
3.9
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
MC9RS08KA8 Series, Rev. 1 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
3.9.1
Num 1 2 3 4 5 6
1 2
Control Timing
Table 10. Control Timing
C D D D D D D Parameter Bus frequency (tcyc = 1/fBus) Real time interrupt internal oscillator period External RESET pulse width KBI pulse width
2 1
Symbol fBus tRTI textrst tKBIPW tKBIPWS
3
Min 0 700 150 1.5 tcyc 100 -- --
Typical -- 1000 -- -- -- 11 35
Max 10 1300 -- -- -- -- --
Unit MHz s ns ns ns ns
KBI pulse width in
stop1
Port rise and fall time (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
tRise, tFall
This is the shortest pulse guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be recognized. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 3 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40C to 85C.
textrst RESET
Figure 17. Reset Timing
tKBIPWS tKBIPW KBI Pin (rising or high level)
KBI Pin (falling or low level) tKBIPW tKBIPWS
Figure 18. KBI Pulse Width
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Electrical Characteristics
3.9.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 11. TPM Input Timing
Num 1 2 3 4 5 C D D D D D Rating External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min DC 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit MHz tcyc tcyc tcyc tcyc
tTCLK tclkh
TCLK tclkl
Figure 19. Timer External Clock
tICPW TPMCHn
TPMCHn tICPW
Figure 20. Timer Input Capture Pulse
3.10
Num 1 2 3 4 5 6 7 8 9
1
Analog Comparator (ACMP) Electrical
Table 12. Analog Comparator Electrical Specifications
C D P D P C C P C P Characteristic Supply voltage Supply current (active) Analog input voltage1 Analog input offset voltage1 Analog Comparator hysteresis1 Analog source impedance1 Analog input leakage current Analog Comparator initialization delay Analog Comparator bandgap reference voltage Symbol VDD IDDAC VAIN VAIO VH RAS IALKG tAINIT VBG 3.0 -- -- -- 1.1 Min 1.80 -- VSS - 0.3 Typical -- 20 -- 20 9.0 -- -- -- 1.208 Max 5.5 35 VDD 40 15.0 10 1.0 1.0 1.3 Unit V A V mV mV k A s V
These data are characterized but not production tested.
MC9RS08KA8 Series, Rev. 1 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
3.11
Num 1 2 3 4 5 6 7 8 C C P C P C C C C
Internal Clock Source Characteristics
Table 13. Internal Clock Source Specifications
Characteristic Average internal reference frequency -- untrimmed Average internal reference frequency -- trimmed DCO output frequency range -- untrimmed DCO output frequency range -- trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature Total deviation of trimmed DCO output frequency over voltage and temperature FLL acquisition time2,3 Stop recovery time (FLL wakeup to previous acquired frequency) IREFSTEN=0 IREFSTEN=1 Symbol fint_ut fint_t fdco_ut fdco_t fdco_res_t fdco_t tacquire Min 25 31.25 12.8 16 -- -- -- Typical1 31.25 39.06 16 20 -- -- -- Max 41.66 39.0625 21.33 20 0.2 2 1 Unit kHz kHz MHz MHz %fdco %fdco ms
t_wakeup
-- 100 86
--
s
1
Data in typical column was characterized at 3.0 V and 5.0 V, 25C or is typical recommended value. This parameter is characterized and not tested on each device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
2
3.12
C D C C C
ADC Characteristics
Table 14. 5 Volt 10-bit ADC Operating Conditions
Characteristic Input voltage Accuracy Input capacitance Input resistance 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) VDD = 2 V Conditions Symb VADIN -- CADIN RADIN Min. VSS -- -- -- -- -- -- 0.4 fADCK 0.4 Typical -- 8 bit 4.5 3 -- -- -- -- -- Max. VDD -- 5.5 5 5 10 10 8.0 MHz 8.0 Unit V -- pF k
C
Analog source resistance external to MCU
RAS
k
D
ADC conversion clock frequency
High Speed (ADLPC=0) Low Power (ADLPC=1)
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21
Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 21. ADC Input Impedance Equivalency Diagram Table 15. 10-bit ADC Characteristics
Characteristic Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply current ADC asynchronous clock source Stop, reset, module off High speed (ADLPC = 0) Low power (ADLPC = 1)
T
Conditions
C
Symb
Min
Typical1
Max
Unit
T
IDDAD
--
133
--
A
T
IDDAD
--
218
--
A
T
IDDAD
--
327
--
A
C
IDDAD
--
0.582
1
mA
T
IDDAD fADACK
-- -- --
0.011 3.3 2
1 --
A MHz
--
MC9RS08KA8 Series, Rev. 1 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 15. 10-bit ADC Characteristics (continued)
Characteristic Conversion time (including sample time) Conditions Short sample (ADLSMP=0) P Long sample (ADLSMP=1) Short sample (ADLSMP=0) Sample time Long sample (ADLSMP=1) 10 bit mode Total unadjusted error 8 bit mode 10 bit mode Differential non-linearity 8 bit mode P DNL T -- C ETUE P tADS tADC C Symb Min -- -- -- -- -- -- -- Typical1 20 40 3.5 23.5 1 0.5 0.5 0.3 Max -- -- -- -- 2.5 1.0 1.0 0.5 Unit ADCK cycles ADCK cycles LSB2
LSB2
Monotonicity and No-Missing-Codes guaranteed 10 bit mode Integral non-linearity 8 bit mode 10 bit mode Zero-scale error 8 bit mode Full-Scale error VADIN = VDDA 10 bit mode 8 bit mode 10 bit mode Quantization error 8 bit mode Input leakage error pad leakage3 * RAS
1
-- C P T P T D EFS EZS INL -- -- -- -- -- -- EQ -- -- D EIL --
0.5 0.3 0.5 0.5 0.5 0.5 -- -- 0.2 0.1
1.0 0.5 1.5 0.5 1.5 0.5 0.5 0.5 2.5 1
LSB2
LSB2
LSB2
LSB2
10 bit mode 8 bit mode
LSB2
Typical values assume Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Based on input pad leakage current. Refer to pad electrical.
3.13
Flash Specifications
Table 16. Flash Characteristics
Characteristic Symbol VDD VPP IVPP_prog IVPP_erase Min 2.7 11.8 -- -- Typical1 -- 12 -- -- Max 5.5 12.2 200 100 Unit V V A A
This section provides details about program/erase times and program-erase endurance for the flash memory. For detailed information about program/erase operations, see the reference manual.
Supply voltage for program/erase Program/Erase voltage VPP current Program Mass erase
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Electrical Characteristics
Table 16. Flash Characteristics (continued)
Characteristic Supply voltage for read operation 0 < fBus < 10 MHz Byte program time Mass erase time Cumulative program HV time2 Total cumulative HV time (total of tme & thv applied to device) HVEN to program setup time PGM/MASS to HVEN setup time HVEN hold time for PGM HVEN hold time for MASS VPP to PGM/MASS setup time HVEN to VPP hold time VPP rise time3 Recovery time Program/erase endurance TL to TH = -40C to 85C Data retention
1 2
Symbol VRead tprog tme thv thv_total tpgs tnvs tnvh tnvh1 tvps tvph tvrs trcv
Min 1.8 20 500 -- -- 10 5 5 100 20 20 200 1 1000
Typical1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 5.5 40 -- 8 2 -- -- -- -- -- -- -- --
Unit V s ms ms hours s s s s ns ns ns s cycles
tD_ret
15
--
years
Typicals are measured at 25C. thv is the cumulative high voltage programming time to the same row before next erase. Same address can not be programmed more than twice before next erase. 3 Fast V PP rise time may potentially trigger the ESD protection structure, which may result in over current flowing into the pad and cause permanent damage to the pad. External filtering for the VPP power source is recommended. An example VPP filter is shown in Figure 22.
100 VPP 12 V 1 nF
Figure 22. Example VPP Filtering
MC9RS08KA8 Series, Rev. 1 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
tprog WRITE DATA1 tpgs
Data Next Data
PGM tnvs HVEN trs VPP2 tnvh trcv
tvps thv
tvph
1 Next 2V DD
Data applies if programming multiple bytes in a single row, refer to MC9RS08KA8 Series Reference Manua must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 23. Flash Program Timing
tme trcv MASS tnvs HVEN trs VPP1
1
tnvh1
tvps
tvph
VDD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 24. Flash Mass Erase Timing
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Electrical Characteristics
3.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 17. Radiated Emissions, Electric Field
Parameter Symbol Conditions Frequency 0.15 - 50 MHz 50 - 150 MHz Radiated emissions, electric field VRE_TEM VDD = TBD TA = 25oC package type TBD 150 - 500 MHz 500 - 1000 MHz IEC Level SAE Level
1
fOSC/fBUS
Level1 (Max) TBD TBD
Unit
dBV
TBD crystal TBD bus
TBD TBD TBD TBD -- --
Data based on qualification test results.
3.14.2
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18.
MC9RS08KA8 Series, Rev. 1 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
Table 18. Conducted Susceptibility, EFT/B
Parameter Symbol Conditions fOSC/fBUS Result A Conducted susceptibility, electrical fast transient/burst (EFT/B) VDD = TBD TA = 25C package type TBD TBD crystal TBD bus B C D
1
Amplitude1 (Min) TBD TBD
Unit
VCS_EFT
kV TBD TBD
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 19. Table 19. Susceptibility Performance Classification
Result A B No failure Self-recovering failure Soft failure Performance Criteria The MCU performs as designed during and after exposure. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation.
C
D
Hard failure
E
Damage
MC9RS08KA8 Series, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Ordering Information
4
Ordering Information
Table 20. Device Numbering System
Memory Device Number Flash RAM Type 16 PDIP MC9RS08KA8 MC9RS08KA4 8K bytes 4K bytes 254 bytes 126 bytes 16 W-SOIC 20 PDIP 20 W-SOIC Designator PG WG PJ WJ Document No. 98ASB42431B 98ASB42567B 98ASB42899B 98ASB42343B Package
This section contains ordering numbers for MC9RS08KA8 series devices. See below for an example of the device numbering system.
MC 9 RS08 KA 8 C XX Status (MC = Fully qualified) Memory (9 = Flash-Based) Core Family Package designator (See Table 20) Temperature range (C = -40C to 85C) Approximate memory size (in KB)
5
* * * *
Mechanical Drawings
16-pin PDIP (plastic dual in-line pin) 16-pin W-SOIC (wide body small outline integrated circuit) 20-pin PDIP (plastic dual in-line pin) 20-pin W-SOIC (wide body small outline integrated circuit)
This following pages contain mechanical specifications for MC9RS08KA8 Series package options.
MC9RS08KA8 Series, Rev. 1 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
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Document Number: MC9RS08KA8
Rev. 1 1/2008
Preliminary--Subject to Change Without Notice

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